Semiconductor Engineering

HSIO Loopback Turns Challenges Into Opportunities For Test At 112 Gbps

For both PCIe and Ethernet (IEEE 802.3,) signals are getting mighty small. With PCIe 5 reaching 32 Gbps (NRZ at 32 GBaud) and 802.3 reaching 112 Gbps (PAM4 at 56 GBaud), typical eye-mask limits are ...
Business Wire

Menlo Micro Releases to Production the 64 Gbps Fully Integrated Loopback Solution for High ...

IRVINE, Calif.--(BUSINESS WIRE)--Menlo Microsystems, Inc. (Menlo Micro), the company responsible for bringing to market the greatest electronic component innovation ...
EDN

Vectorless test: best bet for high-speed I/O

High-volume manufacturers must wrestle with the conundrum of how to cost-effectively test multiple multilane high-speed I/O interfaces-such as PCI Express, HyperTransport and Infiniband-embedded into ...
Electronic Design

Jitter Testing – A High-Throughput Jitter Analysis Test Strategy

A promising solution for economical precision test can take your jitters out of jitter testing. Multigigabit high-speed serial (HSS) interfaces like PCI Express, Fibre Chan-nel, XAUI, and Serial ATA ...