Design-Reuse

Codasip Releases a Major Upgrade of Its Studio Processor Design Toolset with a Tutorial RISC-V core

Munich, Germany – April 13 th, 2021 – Codasip, the leading supplier of processor design solutions and customizable RISC-V processor IP, is pleased to announce the availability of Codasip Studio 9.0 ...
EDN

AXI Interface – Processor Subsystem Hardware Tutorial

This tutorial guides the designer through the three steps required to examine, modify and test the MicroBlaze processor subsystem with the KC705 evaluation board ...
EDN

AXI Interface Embedded Kit MicroBlaze Processor Subsystem Hdw Tutorial

This tutorial guides the designer through the three steps required to examine, modify and test the MicroBlaze processor subsystem with the KC705 evaluation board ...
Digit

Offload over Fabric to Intel Xeon Phi Processor: Tutorial

The OpenMP* 4.0 device constructs supported by the Intel® C++ Compiler can be used to offload a workload from an Intel® Xeon® processor-based host machine to Intel® Xeon Phi™ coprocessors over ...