EDN

Use SystemVerilog for coverage metrics

The design-and-verification industry is at the intersection of two important trends in the design and verification of SOC (system-on-chip) devices: the adoption of SystemVerilog HDVL ...
Design-Reuse

Synopsys Announces Source-Code License for SystemVerilog Verification Library

VMM Standard Library Enables Adoption of Techniques in the ARM-Synopsys Verification Methodology Manual (VMM) for SystemVerilog MOUNTAIN VIEW, Calif. -- Sept. 21, 2005-- Synopsys, Inc., a world leader ...
EDN

SystemVerilog reference verification methodology: RTL

SystemVerilog enables such a unified approach, since code coverage, functional coverage points, and assertions are all defined by the same language. Using formal analysis The VMM for SystemVerilog ...