Design-Reuse

Imperas leads the RISC-V verification ecosystem as the first to release an open-source ...

Complete source file access allows easy adoption and enables user extensions for advanced microarchitecture verification that helps all RISC-V projects accelerate time-to-market goals Design ...
EDN

Use SystemVerilog for coverage metrics

The design-and-verification industry is at the intersection of two important trends in the design and verification of SOC (system-on-chip) devices: the adoption of SystemVerilog HDVL ...
Design-Reuse

Breaking the Language Barriers: Using Coverage Driven Verification to Improve the Quality of IP

Technology advances allows for the creation of larger and more complex designs. This poses new challenges, including efforts to balance verification completeness with minimization of overall ...
New Electronics

Open-source SystemVerilog RISC-V processor functional coverage library

Imperas Software has announced the release of the first open-source SystemVerilog RISC-V processor functional coverage library for RISC-V cores. The initial release is for RV32IMC, RV64 and other ...
Semiconductor Engineering

Three Steps To Low Power Coverage Closure

Low-power design and verification is becoming more complex. Yet it is critical that all power elements are verified, and it is even more important to verify the complex interactions between these ...